`timescale 1ns/1ns
`default_nettype none

module cxy_pixel_display_buf_MBI5353
    #(
    parameter   DW      = 6
    )
    (
    // write
    input  wire          I_wclk,
    input  wire [DW-1:0] I_wren,
    input  wire [8:0]    I_waddr,
    input  wire [15:0]   I_wdata,
    // read
    input  wire          I_rclk,
    input  wire          I_rden,
    input  wire [11:0]   I_raddr,
    output wire [DW-1:0] O_rdata
    );
 
//***********************************************************
localparam  M = DW;

wire            rd_clk;
wire            rd_en;
wire [11:0]     rd_addr;
wire [DW-1:0]      q;

reg  [11:0]     raddr;
reg  [3:0]      rden_sr;
reg  [1:0]      rd_turn;
reg  [DW-1:0]   q_tmp;
//***********************************************************
//-------------------------------------
// instance of dpram_512x32_16384x1
//-------------------------------------
genvar i;
generate
    for(i=0;i<M;i=i+1)
    begin: gen_ram
           // // swsr_512x1_512x1 data_buf (
           // swsr_256x16_4096X1 data_buf(
             // // swsr_64x16_1024X1 data_buf(
           // //   swsr_32x32_1024X1 data_buf(
                // // swsr_16x32_512X1 data_buf(
           // //     swsr_32x16_512X1 data_buf(
                // .clka       (I_wclk     ),
                // .ena        (1'b1       ),
                // .wea        (I_wren[i]  ),
                // .addra      (I_waddr    ),
                // .dina       (I_wdata    ),
                // .clkb       (rd_clk     ),
                // .enb        (rd_en      ),
                // .addrb      (rd_addr    ),
                // .doutb      (q[i]       )
                // );
ad_mem_asym #(
  .A_ADDRESS_WIDTH  (8),
  .A_DATA_WIDTH     (16),
  .B_ADDRESS_WIDTH  (12),
  .B_DATA_WIDTH     (1)
  )
  data_buf (  
                .clka       (I_wclk     ),
                .wea        (I_wren[i]  ),
                .addra      (I_waddr    ),
                .dina       (I_wdata    ),

                .clkb       (rd_clk     ),
  .reb      (rd_en      ),
                .addrb      (rd_addr    ),
                .doutb      (q[i]       )
                );
                
            
// swsr_256x16_4096X1 buf0(
    // .wrclock            ( I_wclk    ),
    // .wren               ( I_wren[i] ),
    // .wraddress          ( I_waddr   ),
    // .data               ( I_wdata   ),
    
    // .rdclock            ( rd_clk    ),
    // .rden               ( rd_en     ),
    // .rdaddress          ( rd_addr   ),
    // .q                  ( q[i]      )
    // );
            
    end
endgenerate
//***********************************************************


     
//raddr[9:0]
always@(posedge I_rclk)
    if(I_rden==1)
        raddr <= I_raddr;

//rd_clk
//rd_en
//rd_addr[11:0]
assign rd_clk  = I_rclk;
assign rd_en   = I_rden ;
assign rd_addr = I_raddr; 


//O_rdata[DW-1:0]

generate
    for(i=0;i<M;i=i+1)
    begin: gen_rdata_h
        assign O_rdata[i] = q[i];
    end
endgenerate
//***********************************************************
endmodule



`default_nettype wire

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